1. Field of the Invention
The invention relates to designing an integrated circuit (IC). More specifically, the invention relates to a method and an apparatus to determine an attribute (which is a design-dependent property) of a portion of a circuit that is affected by changes in one or more parameters resulting from an IC fabrication process (also called “variation” parameters).
2. Related Art
Monte Carlo simulation is a well-known technique of solving any statistical analysis problem such as understanding statistical behavior of an integrated circuit subjected to variation. This technique involves applying random or pseudo-random samples and measures the circuit response to all these samples which allows generation of a statistical representation of the circuit behavior as subjected to variation. See Ashish Srivastava et al, “Statistical Analysis and Optimization for VLSI: Timing and Power”, Springer ISBN 0-387-25738-1. Monte Carlo based techniques are often used as golden results to gauge the accuracy of other approaches. Advantages of Monte Carlo over other techniques are that it is able to handle any non-linear function; there aren't any limitations on the number of variables that Monte Carlo can simulate, and Monte Carlo automatically preserves the correlation among variation parameters.
A variation parameter is a property of an integrated circuit (IC) which changes depending on the fabrication process used to fabricate the IC. Even if the design of the IC is different, the variation parameter can be the same, if the same fabrication process is used. Illustrative examples of the variation parameter include (but are not limited to): channel length, threshold voltage, metal width, metal thickness, dielectric thickness, via resistance, sheet resistivity or PCA (Principal Component Analysis) parameters; where PCA parameters are a smaller set of parameters abstracted out of the physical parameters for the purpose of reducing the number of parameters involved and identifying the major sources of variation. Depending on the effect of these variation parameters they could also be categorized as net parasitics variation, driver cell variation, load cell variation and input slew variation.
An attribute of an integrated circuit is a property which changes depending on the design of the IC. Illustrative examples of attribute include but are not limited to cell delay, cell slew (transition time), net delay, net slew, crosstalk delay, crosstalk slew, arrival windows, timing slack, total net capacitance, total net resistance, effective capacitance, drive resistance, dynamic power, total power, internal power and leakage power.
On chip variational analysis has become more important as the effects of process variation on timing has increased. See S. Nassif, “Delay variability: sources, impact and trends,” ISSCC 2000, pp. 368-369. Process variation occurs in a highly multi-dimensional space. The current inventors note that even without considering intra-die variations, if there are N routing layers, there are at least 4N sources of variation. Thus, even in the most simplified model, not considering intra-die and inter-chip variations, tens of variations have to be considered.
Different variation sources that the current inventors believe should be considered for a stage delay computation are shown in FIG. 1 (prior art). A stage consists of one driver cell and a single interconnect that connects the driver cell to one or more load cells. Note that the load cells after the interconnect are not included in the definition of a stage (as they are included in the next stage). Accordingly, a stage delay does not include delay that occurs entirely within load cells. Instead, in addition to delay within components of a stage, the stage delay includes only the effect of load cells on the aforementioned stage delay. A cell delay is defined as the delay from the input to the output of the driver cell. An interconnect delay is defined as the delay from the output of a driver to the input of a load cell. A stage delay is defined as the addition of a driver cell delay and the interconnect delay.
The current inventors believe that a complete variational analysis should consider different variation sources on driver/load cells 101, 103, cell interconnect 102 and transition time of input signal 104 at the driver cell as shown in FIG. 1. All variation sources have their own probability distributions. In practical designs, these distributions could be of any shape such as normals or lognormals but they are not necessarily limited to Gaussian distributions. The current inventors note that Monte Carlo simulation can handle arbitrary distributions by choosing values from each distribution and running simulations with them. With a sufficiently large number of trial runs, probability distributions of cell delays or interconnect delays can be obtained, for use in IC design validation prior to fabrication.
Many researchers have developed techniques to simplify such analyses by assuming certain characteristics, such as Gaussian distribution for variation sources, or ignoring second order effects by using linear circuit assumptions. Hence, Monte Carlo appears to be a useful technique for analyzing chip devices and interconnects process variation, but its biggest disadvantage is its performance because it requires a large number of trial runs. As a stochastic technique, the error associated to Monte Carlo simulation scales with 1/√{square root over (M)} where M is the number of trials (or samples). When using computers available to today's IC designers, it seems almost impossible to run such a large number of circuit simulations (e.g. using SPICE) in today's multi-million net designs. Accordingly the current inventors have found a need to improve the speed of Monte Carlo simulation while retaining accuracy.